1. Field
Example embodiments relate to methods of manufacturing a semiconductor device. More particularly, example embodiments relate to methods of manufacturing a semiconductor device having a through electrode in a semiconductor substrate.
2. Description of the Related Art
As device speeds and device integration increase, signal delays may also be increased, for example, due to parasitic capacitance introduced by interconnection structures. Advances in integration technology have led to the development of three-dimensional integration, where wafers may be stacked three-dimensionally, in contrast to the conventional two-dimensional approach.
In a three-dimensional wafer stack package (WSP), a technique called through-silicon via (TSV) can be used to extend the via hole through a substrate so that a conductive via for a through electrode may be formed to vertically extend and completely penetrate through the substrate. Such a TSV structure may provide higher speeds, higher integration, and improved functionality in comparison to a long wire pattern interconnection. For example, the conductive via may be formed using copper (Cu) having a low resistance. However, copper is known to have high diffusivity in silicon.
Conventionally, the TSV may be formed through the substrate, prior to back end processing. In particular, the TSV structure may be formed by forming an opening or hole in a substrate (e.g., a silicon substrate). An insulation layer may be formed on the substrate and in the opening. A conductive metal layer (e.g., a copper layer (Cu)) may be formed in the opening, for example, by a plating process or deposition process. A backside of the substrate may then be recessed to expose at least a portion of the conductive metal layer, thereby forming a conductive via extending through the substrate. In this case, the substrate including the conductive via may be exposed repeatedly during processes (e.g., an etch process). Especially, when the portion of the conductive metal layer is exposed during an etch process, the metal of the conductive metal layer (e.g., copper) may diffuse into the substrate to thereby deteriorate a semiconductor device such as a semiconductor chip. Further, a thermal stress may occur due to a thermal expansion difference between the metal and the substrate. Thus, it may be difficult to form the opening having a desired aspect ratio in the substrate. Further, when forming the opening in the substrate, a misalignment problem of the through electrode between an upper wiring may occur.